The present invention relates generally to FET Memory Cells and more particularly to a compact memory cell device and the process for forming the device which includes a capacitor structure within a silicon semiconductor body for charge storage.
A single device memory cell with an FET and a capacitor is described by Dennard in U.S. Pat. No. 3,387,286. The capacitor plates are parallel to the surface of the substrate and occupy a relatively large area of the substrate surface. In an effort to reduce the size of the cell, capacitor structures have been formed within the semiconductor substrate, for example, as described in the article "Capacitor For Single FET Memory Cell", IBM Technical Disclosure Bulletin, Vol. 19, No. 9, Pages 2579-2580, February 1975 where the capacitor is formed in a V-shaped trench filled with polysilicon and co-pending application by Abbas entitled "High Density Single Device Memory Cell", Ser. No. 48,410, filed June 14, 1979, now abandoned, in which the capacitor is formed in a U-shaped trench which is reactively ion etched into the silicon surface. Capacitor structures and charge storage regions formed in trenches in a semiconductor body are also described in U.S. Pat. Nos. 3,962,713 and 4,141,765.